diff options
| author | marcellus <msimon_fr@hotmail.com> | 2025-05-20 15:04:51 +0200 |
|---|---|---|
| committer | marcellus <msimon_fr@hotmail.com> | 2025-05-20 15:04:51 +0200 |
| commit | 3a5f053db27e0342d4ca89ae8771afe5c3966fb0 (patch) | |
| tree | 5f5e6c1bfae7c9856b391381dd625622a043eb6f /CMP | |
| parent | 9cdb6fbadb258a4a04bbe836b0ab3bd39f3f02e7 (diff) | |
update: Tuesday 2 May, 15:04:50 from IUseArchBTW
Diffstat (limited to 'CMP')
| -rw-r--r-- | CMP/Basic Blocks.md | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/CMP/Basic Blocks.md b/CMP/Basic Blocks.md new file mode 100644 index 0000000..af81031 --- /dev/null +++ b/CMP/Basic Blocks.md @@ -0,0 +1,23 @@ +**Block**: Début = label, fin = `jump` ou `cjump`, ni label ni jmp au milieu +# Microprocessors +**ISA** (Instruction Set Architecture) : format, encoding, operations... +## Complex Instruction Set Chip +-> Operations compliquées encapsulées -> plus simple pour l'humain +-> bcp d'instructions +operations n'ont pas toujours la même taille donc plus chiant à exécuter +plusieurs cycles cpu par instruction +## Reduced Instruction Set Chip +One instruction per cycle +### Pipeline d'instruction +Possible parce que les instructions ont tout le temps la même taille +Permet de charger quasi-parallelement les instructions +- Instruction Fetch (IF) +- Instruction Decode (ID) +- Execute (EX) +- Memory Access (MA) +- Write Back (WB) +# MIPS +A simple RISC microprocessor +- N64 +- PlayStation +- Cisco router |
