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authormarcellus <msimon_fr@hotmail.com>2025-05-20 15:04:51 +0200
committermarcellus <msimon_fr@hotmail.com>2025-05-20 15:04:51 +0200
commit3a5f053db27e0342d4ca89ae8771afe5c3966fb0 (patch)
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parent9cdb6fbadb258a4a04bbe836b0ab3bd39f3f02e7 (diff)
update: Tuesday 2 May, 15:04:50 from IUseArchBTW
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+**Block**: Début = label, fin = `jump` ou `cjump`, ni label ni jmp au milieu
+# Microprocessors
+**ISA** (Instruction Set Architecture) : format, encoding, operations...
+## Complex Instruction Set Chip
+-> Operations compliquées encapsulées -> plus simple pour l'humain
+-> bcp d'instructions
+operations n'ont pas toujours la même taille donc plus chiant à exécuter
+plusieurs cycles cpu par instruction
+## Reduced Instruction Set Chip
+One instruction per cycle
+### Pipeline d'instruction
+Possible parce que les instructions ont tout le temps la même taille
+Permet de charger quasi-parallelement les instructions
+- Instruction Fetch (IF)
+- Instruction Decode (ID)
+- Execute (EX)
+- Memory Access (MA)
+- Write Back (WB)
+# MIPS
+A simple RISC microprocessor
+- N64
+- PlayStation
+- Cisco router