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| author | marcellus <msimon_fr@hotmail.com> | 2025-06-06 12:58:10 +0200 |
|---|---|---|
| committer | marcellus <msimon_fr@hotmail.com> | 2025-06-06 12:58:10 +0200 |
| commit | 83c47453ad1705477d707bbf0b1bffa32e057ab1 (patch) | |
| tree | 5b155aab3a7470db9125f5ce71875e342d87acd5 /CMP/Basic Blocks.md | |
| parent | 147394e7692bdf77f041e4b9bd9ff0daac1ee9c7 (diff) | |
| parent | 07ca5a5d24c7aa87c923e9bd6091480ad407827a (diff) | |
Merge remote-tracking branch 'origin/master'
Diffstat (limited to 'CMP/Basic Blocks.md')
| -rw-r--r-- | CMP/Basic Blocks.md | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/CMP/Basic Blocks.md b/CMP/Basic Blocks.md new file mode 100644 index 0000000..f145d8b --- /dev/null +++ b/CMP/Basic Blocks.md @@ -0,0 +1,25 @@ +**Block**: Début = label, fin = `jump` ou `cjump`, ni label ni jmp au milieu +# Microprocessors +**ISA** (Instruction Set Architecture) : format, encoding, operations... +## Complex Instruction Set Chip +-> Operations compliquées encapsulées -> plus simple pour l'humain +-> bcp d'instructions +operations n'ont pas toujours la même taille donc plus chiant à exécuter +plusieurs cycles cpu par instruction +## Reduced Instruction Set Chip +One instruction per cycle +### Pipeline d'instruction +Possible parce que les instructions ont tout le temps la même taille +Permet de charger quasi-parallelement les instructions +- Instruction Fetch (IF) +- Instruction Decode (ID) +- Execute (EX) +- Memory Access (MA) +- Write Back (WB) +# MIPS +A simple RISC microprocessor +- N64 +- PlayStation +- Cisco router +# Instruction Selection +AST -> Assembly
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