summaryrefslogtreecommitdiff
path: root/CMP/Basic Blocks.md
diff options
context:
space:
mode:
authormarcellus <msimon_fr@hotmail.com>2025-06-06 12:58:10 +0200
committermarcellus <msimon_fr@hotmail.com>2025-06-06 12:58:10 +0200
commit83c47453ad1705477d707bbf0b1bffa32e057ab1 (patch)
tree5b155aab3a7470db9125f5ce71875e342d87acd5 /CMP/Basic Blocks.md
parent147394e7692bdf77f041e4b9bd9ff0daac1ee9c7 (diff)
parent07ca5a5d24c7aa87c923e9bd6091480ad407827a (diff)
Merge remote-tracking branch 'origin/master'
Diffstat (limited to 'CMP/Basic Blocks.md')
-rw-r--r--CMP/Basic Blocks.md25
1 files changed, 25 insertions, 0 deletions
diff --git a/CMP/Basic Blocks.md b/CMP/Basic Blocks.md
new file mode 100644
index 0000000..f145d8b
--- /dev/null
+++ b/CMP/Basic Blocks.md
@@ -0,0 +1,25 @@
+**Block**: Début = label, fin = `jump` ou `cjump`, ni label ni jmp au milieu
+# Microprocessors
+**ISA** (Instruction Set Architecture) : format, encoding, operations...
+## Complex Instruction Set Chip
+-> Operations compliquées encapsulées -> plus simple pour l'humain
+-> bcp d'instructions
+operations n'ont pas toujours la même taille donc plus chiant à exécuter
+plusieurs cycles cpu par instruction
+## Reduced Instruction Set Chip
+One instruction per cycle
+### Pipeline d'instruction
+Possible parce que les instructions ont tout le temps la même taille
+Permet de charger quasi-parallelement les instructions
+- Instruction Fetch (IF)
+- Instruction Decode (ID)
+- Execute (EX)
+- Memory Access (MA)
+- Write Back (WB)
+# MIPS
+A simple RISC microprocessor
+- N64
+- PlayStation
+- Cisco router
+# Instruction Selection
+AST -> Assembly \ No newline at end of file